1. Field of the Invention
The present invention generally relates to the design and manufacture of integrated circuits such as application specific integrated circuits (ASICs) and, more specifically, to efficient usage of chip space allocated to logic cells and input/output (I/O) cells thereof.
2. Description of the Prior Art
The use of digital data processing has become ubiquitous, particularly for control and data gathering functions. Many common commercial products now include at least one if not dozens of digital processors for control of at least some operations or operating conditions thereof. In other cases, collected raw data must be processed using a complex computation in order to be of use. Many circumstances are thus presented in which some particular digital processing algorithms must be rapidly performed repeatedly and to the exclusion of a general capability for performance of arbitrary algorithms. Additionally, processing speed requirements may exceed that which is available from general purpose processing circuits which are commercially available.
In such a case, or for reasons of physical (e.g. size, weight or power consumption) constraints, it is usually necessary to design and fabricate one or more application specific integrated circuits (ASICs) which may be of limited processing capability compared to general purpose processors but which may be optimized to provide the particular functions needed. In general, the design and fabrication of integrated circuits is prohibitively expensive unless the quantity of identical circuits which can be commercially marketed is very large, often one million or more, to allow the design cost to be distributed over a large number of chips. Therefore, to support the design of ASICs which are typically produced in less than commercial quantities (e.g. ten thousand or, sometimes, much less), some design techniques and standardized portions of chip designs such as chip sizes and power and signal input and output layouts, collectively referred to as a chip image, have been developed to reduce the amount of design and layout effort required for a new ASIC design. All such design portions must be fully documented to insure compatibility with other features of the design.
Even at a more basic level, ASIC designs are usually carried out using standardized cells. A cell, as the term is used herein, is an electronic element of pattern therefor such as a transistor or capacitor or an elemental logic circuit such as an inverter, driver, power converter or transmission or logic gate which can be repeated as necessary in combination with other cells to build up a circuit design corresponding to the desired function. These cell designs must also be fully documented.
In practice, some groups of cells are often used together and the same group of cells may be used in different configurations depending on placement on a chip and referred to by either the function (e.g. logic, power, I/O, etc.) or placement (e.g. edge, corner etc.) of the group of cells. Thus the group of cells may be repeated a number of times on a chip and used as a group in different ASIC designs in much the same manner as individual cells for convenience in design development. Such a group of cells may also be referred to as a cell and may, like simpler or more elemental cells, be further identified by placement and/or function. In general, I/O cells are placed around the periphery of chips with connection pads forming a so-called pad collar.
The documentation of images and other standardized features which may be included in a given design is, itself, costly but justified in supporting the ability to design ASICs at an acceptable cost. In particular, this relatively massive amount of information, often referred to as libraries, can be rapidly and automatically accessed by computers to rapidly develop chip layouts and manufacturing mask patterns with very limited operator intervention. A library must be established for each technology (e.g. bipolar transistors, CMOS, and the like and each type of perfecting feature employed therewith, each minimum feature size regime, each function of respective cell types, each size and shape of chip, each package design and so on) used in integrated circuit designs.
However, such processing to create a new chip design is optimally effective only to the extent that the design is constrained to use of standardized design features and previously designed cells. The resulting design is not optimized to produce the design using the smallest possible chip size. Since costs of manufacture depend on the number of chips which can be formed on a single wafer on which a sequence of processing steps are performed using very expensive tools (e.g. lithographic exposure tools, plasma reactors, annealing chambers and the like) chip size may have a major impact on overall production costs of ASICs, notwithstanding the economies which may have been achieved in design using standardized documentation libraries.
Such an impact is particularly evident since many wirebond ASIC chips are not I/O (input/output) limited. That is, the image/package can support more I/Os (e.g. I/O cells) than the design requires while the internal core logic of the design dictates the chip/package size. I/O sites on the image are typically occupied by I/O cells and the unused I/O sites are essentially wasted chip space. Moreover, I/O cells tend to be very large compared to logic cells or other types of cells and, depending on the number of unused I/O sites, this wasted space can be a significant proportion of the area of the die or chip.
Since the cost to make a die is proportional to the area of the die (e.g. limiting the number of dies which can be fabricated on a wafer of a given size using a given number of wafer processing steps), it is desirable to make the die as small as possible by adjusting the I/O site layout even though such an adjustment is a departure from standardized design features. Two alternative techniques for performing such an adjustment are currently known and both involve adjustment of I/O pitch and wirebond pad pitch.
A first technique for adjustment of I/O cell layout starts with a staggered wirebond pad pattern of a standard image and removes one of the rows of wirebond pads and relaxing (e.g. substantially doubling) the pitch of wirebond pads. When used with the same I/O cell library with the same aspect ratio as in the standard image, the result is that fewer (often about half) of the I/O sites are bonded out from the chip to the package.
A second technique is to change the I/O cell aspect ratio, and change the wirebond pad pitch accordingly, to produce either a staggered or in-line pad collar on the chip. This approach reclaims more chip space than the first technique described above but requires costly development and maintenance of additional I/O cell libraries (e.g. for each different I/O cell aspect ratio) for each I/O cell to wirebond pad pitch relationship.
While these techniques can potentially reclaim some space on a chip which would be otherwise wasted and could potentially allow a smaller chip size to be employed, the possibility of using a smaller chip may not become evident until a particular design is relatively advanced after expenditure of substantial design time and expense. Further, use of an optimally small chip is not guaranteed. At the present state of the art, no process is known which can optimize the chip size of a design based on the number of I/O cells required by the design.